TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-10 V2.0, 2007-07
FADC, V2.0
Table 26-2 describes the possible gating modes (enabled, disabled, active gating
source input polarity) of an FADC channel.
An edge detection unit determines which edge of the trigger source input signal (as
selected by CFGRx.TSEL) is generating a conversion request trigger signal. Rising,
falling or both edges can be selected for trigger signal generation.
The Conversion Request Flag CRFx is cleared by hardware when the conversion of
channel x is started. CRFx can also be set or cleared by software via bits in the Flag
Modification Register FMR. Writing a 1 to FMR.SCRF sets CRFx. Writing a 1 to
FMR.RCRF clears CRFx (independently of FMR.SCRF).
Table 26-2 Gating Modes
CFGRx.GM Gating Mode
00
B
Conversion requests are disabled and Channel Timer is stopped.
CRFx never becomes set (by hardware).
01
B
Conversion requests and Channel Timer are always enabled. CRFx
becomes set by hardware with each active trigger signal.
10
B
When gating source input GSn = 1 (as selected by CFGRx.GSEL),
the Channel Timer is enabled and the conversion request flag CRFx
becomes set by hardware with each active trigger signal.
11
B
When gating source input GSn = 0 (as selected by CFGRx.GSEL),
the Channel Timer is enabled and the conversion request flag CRFx
becomes set by hardware with each active trigger signal.
Table 26-3 Trigger Modes
CFGRx.TM Trigger Mode
00
B
No trigger signal generated. Edge detection unit always delivers a 0.
01
B
A conversion request trigger signal is generated on a rising edge of
trigger source input TSn (as selected by CFGRx.TSEL).
10
B
A conversion request trigger signal is generated on a falling edge of
trigger source input TSn (as selected by CFGRx.TSEL).
11
B
A conversion request trigger signal is generated on a rising or falling
edge of trigger source input TSn (as selected by CFGRx.TSEL).
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