TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-12 V2.0, 2007-07
SSC, V2.1
20.1.2.6 Transmit FIFO Operation
The Transmit FIFO (TXFIFO) provides the following functionality:
• Enable/disable control
• Programmable filling level for transmit interrupt generation
• Filling level indication
• FIFO clear (flush) operation
• FIFO overflow error generation
• 2 to 16 bit TXFIFO data width
The TXFIFO is controlled by the TXFCON control register. When bit TXFCON.TXFEN is
set, the TXFIFO is enabled. The interrupt trigger level defined by TXFCON.TXFITL
determines the filling level of the TXFIFO at which a transmit interrupt TIR is generated.
This interrupt is always generated when the filling level of the TXFIFO is equal to or less
than the value stored in TXFCON.TXFITL.
Bit field TXFFL in the FIFO Status Register FSTAT indicates the number of entries that
are actually written (valid) in the TXFIFO. Therefore, the software can verify in the
interrupt service routine, for instance, how many bytes can be still written into the
TXFIFO via register TB without getting an overrun error.
The TXFIFO cannot be accessed directly. All data write operations to the TXFIFO are
executed by writing into the TB register. The data width of one TXFIFO stage can be from
2 to 16 bits (as programmed in CON.BM).
Figure 20-6 shows an example of a TXFIFO operation with a typical data width of 8 bits,
representing a byte. In this example, seven bytes are transmitted via the transmit output
line. The TXFIFO interrupt trigger level TXFCON.TXFITL is set to 0011
B
. The first byte
written into the empty TXFIFO via TB is directly transferred into the transmit shift register
and is not written into the FIFO. After Byte 1, Bytes 2 to 6 are written into the TXFIFO.
After the transfer of Byte 3 from the TXFIFO into the transmit shift register of the SSC,
3 bytes remain in the TXFIFO. Therefore, the value of TXFCON.TXFITL is reached and
a transmit buffer interrupt will be generated at the beginning and a transmit interrupt at
the end of the Byte 3 serial transmission. During the serial transmission of Byte 4,
another message (Byte 7) is written into the TXFIFO (TB write operation). Finally, after
the start of the serial transmission of Byte 7, the TXFIFO is again empty.
If the TXFIFO is full and additional bytes are written into TB, the transmit interrupt will be
generated with bit CON.TE set if bit CON.TEN was set. In this case, the data that was
last written into the TXFIFO is overwritten and the TXFIFO filling level FSTAT.TXFFL is
set to maximum.
The TXFIFO can be flushed or cleared by setting bit TXFCON.TXFFLU. After this
TXFIFO flush operation, the TXFIFO is empty and the TXFIFO filling level FSTAT.TXFFL
is set to 0000
B
. A running serial transmission is not aborted by a RXFIFO flush operation.
To Next Page
Loading...
Need help?
General