TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-74 V2.0, 2007-07
Ports, V2.0
10.11.3.5 Port 8 Pad Driver Mode Register and Pad Classes
The Port 8 pad driver mode register contains two bit fields that determine the pad driver
mode (output driver strength and slew rate) of Port 8 lines and line groups. The Port 8
port lines are assigned to A1 and A2 pad classes (see also Figure 10-12).
P8_PDR
Port 8 Pad Driver Mode Register (40
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0PDMLI1
rrw
1514131211109876543210
0PD0
rrw
Field Bits Type Description
PD0 [2:0] rw Pad Driver Mode for P8.1, P8.4, P8.6, and P8.7
(Class A1 pads; for coding see Page 10-11)
PDMLI1 [18:16] rw Pad Driver Mode for P8.0, P8.2, P8.3, and P8.5
(Class A2 pads; for coding see Page 10-11)
0 [15:3],
[31:19]
r Reserved
Read as 0; should be written with 0.
To Next Page
Loading...
Need help?
General