TC1796
System Units (Vol. 1 of 2)
System Timer
User’s Manual 15-6 V2.0, 2007-07
STM, V2.0
A compare operation with MSIZE not equal 0 always implies that the compared value
stored in the CMP register is right-extended with zeros. This means that in the example
of Figure 15-2, the compare register content STM_CMP0[17:0] plus ten zero bits right-
extended is compared with STM[27:0] with STM[9:0] = 000
H
. In case of register
STM_CMP1, STM[14:0] with STM[6:0] = 00
H
are compared to STM_CMP1[7:0] plus
seven zero bits right-extended.
15.2.3 Compare Match Interrupt Control
The compare match interrupt control logic is shown in Figure 15-3. Each STM_CMPx
register has its compare match interrupt request flag (STM_ICR.CMPxIR) that is set by
hardware on a compare match event. The interrupt request flags can be set
(STM_ISSR.CMPxIRS) or cleared (STM_ISSR.CMPxIRR) by software. Note that setting
STM_ICR.CMPxIR by writing a 1 into STM_ISSR.CMPxIRS does not generate an
interrupt at STMIRx. The compare match interrupts from CMP0 and CMP1 can be further
directed by STM_ICR.CMPxOS to either output signal STMIR0 or STMIR1. The STMIR0
and STMIR1 outputs are each connected to an interrupt service request control
registers, STM_SRC0 and STM_SCR1. These registers control the general interrupt
handling and processing as described in Chapter 14 of this TC1796 System Units (Vol.
1 of 2) User’s Manual.
Figure 15-3 STM Interrupt Control
MCA05748_mod
Compare Match
from CMP0
Register Set
CMP0
IR
CMP0
OS
CMP0
EN
CMP1
IR
CMP1
OS
CMP1
EN
Compare Match
from CMP1
Register Set
0
1
0
1
STMIR0
STMIR1
STM_ICR Register
CMP0
IRR
CMP1
IRR
CMP1
IRS
CMP0
IRS
STM_ISRR Reg.
Set
Clear
Set
Clear
≥1
≥1
To Next Page
Loading...
Need help?
General