TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-68 V2.0, 2007-07
Ports, V2.0
10.10.3 Port 7 Registers
The following registers are available on Port 7:
Note: The complete address map of Port 7 is described in Table 18-16 on Page 18-29
of this TC1796 System Units (Vol. 1 of 2) User’s Manual.
10.10.3.1 Port 7 Output Register
The basic P7_OUT register functionality is described on Page 10-13. Port lines P7.[15:8]
are not available. Therefore, the P7_OUT bits P[15:8] should be written with 0, and are
always read as 0.
10.10.3.2 Port 7 Output Modification Register
The basic P7_OMR register functionality is described on Page 10-14. Port lines
P7.[15:8] are not available. Therefore, the P7_OMR bits PS[15:8] and PR[15:8] are not
implemented. These bits should always be written with 0.
10.10.3.3 Port 7 Input Register
The basic P7_IN register functionality is described on Page 10-17. Port lines P7.[15:8]
are not available. Therefore, the P7_IN bits P[15:8] are always read as 0.
Table 10-22 Port 7 Registers
Register
Short Name
Register Long Name Offset
Address
Description
see
P7_OUT Port 7 Output Register 0000
H
below
1)
1) These registers are listed and noted here in the Port 7 section because they differ from the general port
register description given in Section 10.2.
P7_OMR Port 7 Output Modification Register 0004
H
P7_IOCR0 Port 7 Input/Output Control Register 0 0010
H
Page 10-7
P7_IOCR4 Port 7 Input/Output Control Register 4 0014
H
Page 10-8
P7_IN Port 7 Input Register 0024
H
below
1)
P7_PDR Port 7 Pad Driver Mode Register 0040
H
Page 10-69
1)
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