TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual 25-103 V2.0, 2007-07
ADC, V2.0
25.3.3 Clock Control
The ADC0/ADC1 modules are provided with common clock signals:
• f
CLC
This is the module control clock that is used inside the ADC0/ADC1 kernels for
control purposes such as e.g. for clocking of control logic and register operations.
The frequency of f
CLC
is equal to the system clock frequency f
SYS
. The clock control
register ADC0_CLC makes it possible to enable/disable
f
CLC
under certain
conditions.
•
f
ADC
This clock is the module timing clock that is used in the ADC0/ADC1 kernels as basic
and timing reference clock for the analog part. The fractional divider registers
ADC0_FDR controls the frequency of f
ADC
and makes it possible to enable/disable it
independently of f
CLC
. The fractional divider’s external clock enable feature is not
used.
Signal RST_EXT_DIV of the fractional divider which is controlled by bit fields SC and DM
of the ADC0_FDR register makes it possible to put the analog parts of the ADCs in its
reset state. When setting ADC0_FDR.SC = 11
B
(and afterwards back to the previous
state of ADC0_FDR.SC), the analog parts of ADC0 and ADC1 are reset. This feature
makes it possible, for example, to start a power-up calibration without a reset operation
of the complete ADCs.
Figure 25-32 ADC0/ADC1 Clock Generation
MCA06035
Clock Control
Register
ADC0_CLC
f
CLC
ADC Clock Generation
f
ADC
f
SYS
Fractional Divider
Register
ADC0_FDR
ADC0
Module
Kernel
ECEN
ADC1
Module
Kernel
V
SS
RST_EXT_DIV
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