TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-213 V2.0, 2007-07
MultiCAN, V2.0
22.9.6 Parity Protection for CAN Memories
In the TC1796, the static RAM memories in the MultiCAN module which include
message objects and TTCAN scheduler entries, are equipped with a parity error
detection logic that makes it possible to detect parity errors. In case of a parity error a
NMI is generated.
At a power-on reset operation the corresponding MultiCAN module memories are
initialized automatically. Therefore, unlike other TC1796 on-chip memories the MultiCAN
module memories must not be initialized by a user program before it can be enabled for
parity error detection.
More details on the parity control for on-chip memories is described in Section 5.5 on
Page 5-37.
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