Infineon Technologies TC1796 - 26.2.4 Filter Registers

TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-48 V2.0, 2007-07
FADC, V2.0
26.2.4 Filter Registers
Filter blocks 0 and 1 are controlled by bits in the Filter n Control Registers FCRn.
FCRn (n = 0-1)
Filter n Control Register (60
H
+n*20
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
IEN 0 INP 0 INSEL 0 MAVL 0 ADDL
rwrrwr rw r rwr rw
Field Bits Type Description
ADDL [2:0] rw Addition Length
This bit field determines the number of filter input
values that are added to obtain one intermediate
result.
000
B
Each filter input value is considered as
intermediate result.
001
B
2 filter input values are added up.
010
B
3 filter input values are added up.
011
B
4 filter input values are added up.
100
B
5 filter input values are added up.
101
B
6 filter input values are added up.
110
B
7 filter input values are added up.
111
B
8 filter input values are added up.