Infineon Technologies TC1796 - Page 2100

TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-49 V2.0, 2007-07
FADC, V2.0
MAVL [5:4] rw Moving Average Length
This bit field determines the number of intermediate
results that are added up for a final result.
00
B
No moving average is selected. Each
intermediate result is considered as final result
value: FRRn.FR = CRRn.CR
01
B
A moving average of 2 values is selected.
The final result is calculated by 2 values:
FRRn.FR = CRRn.CR + IRR1n.IR
10
B
A moving average of 3 values is selected.
The final result is calculated by 3 values:
FRRn.FR = CRRn.CR + IRR1n.IR + IRR2n.IR
11
B
A moving average of 4 values is selected.
The final result is calculated by 4 values:
FRRn.FR = CRRn.CR + IRR1n.IR + IRR2n.IR
+ IRR3n.IR
Bit combinations 10
B
and 11
B
are not available in
filter block 1.
INSEL [10:8] rw Input Selection
This bit field enables the filter block and determines
which input value is taken for filter block n.
000
B
The filter block is disabled. Intermediate and
final sum calculations are not executed. The
filter register values are not changed (except
by a filter block reset).
001
B
Any conversion result of each channel is taken
as new filter input value.
010
B
Filter block 0: filter is stopped (as 000
B
).
Filter block 1: filter input value is the output
value (final result) of filter block 0.
011
B
Reserved
100
B
Channel 0 conversion result is taken as filter
input value.
101
B
Channel 1 conversion result is taken as filter
input value.
110
B
Channel 2 conversion result is taken as filter
input value.
111
B
Channel 3 conversion result is taken as filter
input value.
Field Bits Type Description