TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-22 V2.0, 2007-07
Ports, V2.0
10.3.3 Port 0 Registers
The following registers are available on Port 0:
Note: The complete address map of Port 0 is described in Table 18-9 on Page 18-22 of
this TC1796 System Units (Vol. 1 of 2) User’s Manual.
Table 10-7 Port 0 Registers
Register
Short Name
Register Long Name Offset
Address
Description
see
P0_OUT Port 0 Output Register 0000
H
Page 10-13
P0_OMR Port 0 Output Modification Register 0004
H
Page 10-14
P0_IOCR0 Port 0 Input/Output Control Register 0 0010
H
Page 10-7
P0_IOCR4 Port 0 Input/Output Control Register 4 0014
H
Page 10-8
P0_IOCR8 Port 0 Input/Output Control Register 8 0018
H
Page 10-8
P0_IOCR12 Port 0 Input/Output Control Register 12 001C
H
Page 10-9
P0_IN Port 0 Input Register 0024
H
Page 10-17
P0_PDR Port 0 Pad Driver Mode Register 0040
H
Page 10-23
1)
1) This register is listed here in the Port 0 section because they differ from the general port register description
given in Section 10.2.
SCU_SCLIR SCU Software Configuration Latched Inputs
Register
2)
2) This register is located in the address range of the SCU.
Page 10-24
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