TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-57 V2.0, 2007-07
EBU, V2.0
13.8.6 Dynamic Command Delay and Wait State Insertion
In general, there are two critical phases during asynchronous device accesses. These
phases are:
• Command Delay Phase (see Page 13-43).
• Command Phase (see Page 13-43).
In the EBU, internal length programming for these two phases is available via bit field
EBU_BUSAPx.CMDDELAY. This bit field determines the basic number of Command
Delay phase clock cycles. The total number of Command Delay phase clock cycles
further depends on the settings of bit field EBU_BUSCONx.CMULT and
EBU_BUSCONx.MULTMAP[2].
The equivalent control capability is available for bit fields EBU_EMUBAP.CMDDELAY,
EBU_EMUBCx.CMULT, and EBU_EMUBCx.MULTMAP[2]. The WAIT functionality as
described in the next two subsections, has also an equivalent control capability for the
bit fields EBU_EMUBC.CMDDELAY, EBU_EMUAP.WAITRDC, and
EBU_EMUAP.WAITWRC.
13.8.6.1 External Extension of the Command Phase by WAIT
The WAIT input can be used to cause the EBU to extend the Command Phase by
inserting additional cycles prior to deactivation of the RD and RD/WR lines. This signal
can be programmed separately for each region to be ignored or sampled either
synchronously or asynchronously (selected via the EBU_BUSCONx.WAIT or
EBU_EMUBC.WAIT bit field). Additionally, the polarity of WAIT can be programmed for
active low (default after reset) or active high function via bit EBU_BUSCONx.WAITINV
or EBU_EMUBC.WAITINV. The signal will only take effect after the programmed number
of Command Phase cycles has passed. This means that the signal can only be used to
extend the phase, not to shorten it.
When programmed for synchronous operation, WAIT is sampled on every rising edge of
LMBCLK during the Command Phase. The sampled value is then used on the next rising
edge of LMBCLK to decide whether to prolong the Command Phase or to start the next
phase. Figure 13-20 shows an example of WAIT used in Synchronous Mode.
Note: Due to the one-cycle delay in Synchronous Mode between the sampling of the
WAIT input and its evaluation by the EBU, the Command Phase must always be
programmed to be at least one LMBCLK cycle (via EBU_BUSAPx.WAITRDC or
EBU_BUSAPx.WAITWRC) in this mode.
When programmed for asynchronous operation, WAIT is also sampled at each rising
edge of LMBCLK during the Command Phase. However, an extra synchronization cycle
is inserted prior to the use of the sampled value. This means that the sampled value is
not used until the second following rising edge of LMBCLK. Figure 13-21 shows an
example of WAIT used in Asynchronous Mode.
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