TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-74 V2.0, 2007-07
MSC, V2.0
21.3.4.2 Pad Driver Mode Registers
The Port 5 and Port 9 pad driver mode registers contain bit fields that determine the
output driver strength and the slew rate of MSC output lines.
P5_PDR
Port 5 Pad Driver Mode Register (40
H
) Reset Value: 0000 0000
H
31 30 28 26 24 0
0
PD
MSC1
0
PD
MSC0
0
PD
ASC1
0
PD
ASC0
0
rrwrrwr rw r rw r
Field Bits Type Description
PDMSC0 [26:24] rw Pad Driver Mode for P5.4/EN00
1)
1) Coding of bit field see Table 21-12. Shaded bits and bit fields are “don’t care” for MSC I/O port control.
PDMSC1 [30:28] rw Pad Driver Mode for P5.6/EN10
1)
P9_PDR
Port 9 Pad Driver Mode Register (40
H
) Reset Value: 0000 0000
H
31 22 20 18 16 2 0
0
PD
MSC1
0
PD
MSC0
0PD0
rrwrrw rrw
Field Bits Type Description
PD0 [2:0] rw Pad Driver Mode for P9.8/FCLP0B
1)
1) Coding of bit field see Table 21-12. Shaded bits and bit fields are “don’t care” for MSC I/O port control.
PDMSC0 [18:16] rw Pad Driver Mode for P9.7/SOP0B, P9.6/EN01,
P9.5/EN02, P9.4/EN03
1)
PDMSC1 [22:20] rw Pad Driver Mode for P9.3/FCLP1B, P9.2/SOP1B,
P9.1/EN11, P9.0/EN12
1)
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