TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-3 V2.0, 2007-07
Buses, V2.0
6.1.2 Transaction Types
6.1.2.1 Single Transfers
Single transfers are all transactions that are initiated by any instruction (code or data) of
the TriCore 1 CPU and that require a system resource which not part of the TriCore 1
PMI or DMI. The only exceptions are the following instructions:
• LDMST, ST.T and SWAP.W generate atomic transfers
• Cache miss instructions generate block transfers
6.1.2.2 Block Transfers
Block transfers are only issued in two ways:
1. By the PMI in case of a cache miss.
2. By the PCP if it uses a BCOPY instruction.
Block transfers work in the same way as single transfers, except that only one address
phase with two or four data phases is generated.
6.1.2.3 Atomic Transfers
Atomic transfers are initiated by instructions that require two single transfers (e.g. read-
modify-write instructions such as LDMST, ST.T and SWAP.W). During an atomic
transfer, any other LMB master is blocked for gaining bus ownership.
6.1.3 Address Alignment Rules
Depending on the data size, there are rules that determine the address alignment of an
LMB transfer.
1. Byte accesses must be always located on byte address boundaries.
2. Half-word accesses must be aligned to addresses with address line A0 = 0.
3. Word accesses must be aligned to addresses with address lines A[1:0] = 00
B
.
4. Double-word accesses must be aligned to addresses with address lines
A[2:0] = 000
B
.
5. Block transfers must be aligned identical as double-word addresses.
6.1.4 Reaction of a Busy Slave
If an LMB slave is busy at an incoming LMB transaction request, it can delay the
execution of the LMB transaction. The requesting LMB master releases the LMB for one
cycle after the LMB transaction request in order to allow the LMB slave to indicate if it is
ready to handle the requested LMB transaction.
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