Infineon Technologies TC1796 - 10.4.3.1 Port 1 Pad Driver Mode Register and Pad Classes

TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-31 V2.0, 2007-07
Ports, V2.0
Note: The complete address map of Port 1 is described in Table 18-10 on Page 18-23
of this TC1796 System Units (Vol. 1 of 2) User’s Manual.
10.4.3.1 Port 1 Pad Driver Mode Register and Pad Classes
The Port 1 pad driver mode register contains four bit fields that determine the pad driver
mode (output driver strength and slew rate) of Port 1 lines and line groups. The Port 1
port lines are assigned to A1 and A2 pad classes (see also Figure 10-5).
P1_PDR
Port 1 Pad Driver Mode Register (40
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 PDSYSCLK 0 PDMLI0
rrwrrw
1514131211109876543210
0 PD10PD0
rrwrrw
Field Bits Type Description
PD0 [2:0] rw Pad Driver Mode for P1.[3:0] and P1.[15:13]
(Class A1 pads; for coding see Page 10-11)
PD1 [6:4] rw Pad Driver Mode for P1.5. P1.8, P1.[11:10]
(Class A1 pads; for coding see Page 10-11)
PDMLI0 [18:16] rw Pad Driver Mode for P1.4, P1.[7:6], P1.9
(Class A2 pads; for coding see Page 10-11)
PDSYSCLK [22:20] rw Pad Driver Mode for P1.12
(Class A2 pads; for coding see Page 10-11)
0 3, 19,
[15:7],
[31:23]
r Reserved
Read as 0; should be written with 0.