Infineon Technologies TC1796 - Page 1012

TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-23 V2.0, 2007-07
Regs, V2.0
Table 18-10 Address Map of Port 1
Short Name Description Address Access Mode Reset Value
Read Write
Port 1
P1_OUT Port 1 Output Register F000 0D00
H
U, SV U, SV 0000 0000
H
P1_OMR Port 1 Output
Modification Register
F000 0D04
H
U, SV U, SV,
32
0000 XXXX
H
– Reserved F000 0D08
H
-
F000 0D0C
H
U, SV U, SV –
P1_IOCR0 Port 1 Input/Output
Control Register 0
F000 0D10
H
U, SV U, SV 2020 2020
H
P1_IOCR4 Port 1 Input/Output
Control Register 4
F000 0D14
H
U, SV U, SV 2020 2020
H
P1_IOCR8 Port 1 Input/Output
Control Register 8
F000 0D18
H
U, SV U, SV 2020 2020
H
P1_IOCR12 Port 1 Input/Output
Control Register 12
F000 0D1C
H
U, SV U, SV 2020 2020
H
– Reserved F000 0D20
H
U, SV U, SV –
P1_IN Port 1 Input Register F000 0D24
H
U, SV U, SV 0000 XXXX
H
– Reserved F000 0D28
H
-
F000 0D3C
H
U, SV U, SV –
P1_PDR Port 1 Pad Driver Mode
Register
F000 0D40
H
U, SV SV, E 0000 0000
H
– Reserved F000 0D44
H
-
F000 0DFC
H
U, SV U, SV –