TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-58 V2.0, 2007-07
Ports, V2.0
10.8.3.4 Port 5 Pad Driver Mode Register and Pad Classes
The Port 5 pad driver mode register contains four bit fields that determine the pad driver
mode (output driver strength and slew rate) of Port 5 line groups. The Port 5 port lines
are all class A2 pads (see also Figure 10-9).
P5_PDR
Port 5 Pad Driver Mode Register (40
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 PDMSC1 0 PDMSC0 0 PDASC1 0 PDASC0
rrwrrwrrwrrw
1514131211109876543210
0
r
Field Bits Type Description
PDASC0 [18:16] rw Pad Driver Mode for P5.[1:0]
(Class A2 pads; for coding see Page 10-11)
PDASC1 [22:20] rw Pad Driver Mode for P5.[3:2]
(Class A2 pads; for coding see Page 10-11)
PDMSC0 [26:24] rw Pad Driver Mode for P5.[5:4]
(Class A2 pads; for coding see Page 10-11)
PDMSC1 [30:28] rw Pad Driver Mode for P5.[7:6]
(Class A2 pads; for coding see Page 10-11)
0 [15:0],
19, 23,
27, 31
r Reserved
Read as 0; should be written with 0.
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