TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-55 V2.0, 2007-07
PCP, V2.0
11.10.2 PCP Clock Control Register, PCP_CLC
PCP_CLC
PCP Clock Control Register (00
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
PCG
DIS
0
rw r
Field Bits Type Description
PCGDIS 15 rw Clock Gating Disable Bit
Allows clock gating to be disabled.
0
B
PCP Internal Clock stops when PCP is idle
(default after reset)
1
B
PCP Internal Clock always runs
0 [14:0],
[31:16]
r Reserved
Read as 0; should be written with 0.
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