TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-85 V2.0, 2007-07
Ports, V2.0
10.14.2 LVDS Outputs of MSC0 and MSC1
The clock and data output lines of MSC0 and MSC1 are connected to dedicated
differential output drivers, each of which has positive and negative signal polarity. These
types of 3.3V LVDS pads are assigned as class C pads.
The LVDS outputs are controlled by a bit LDEN (LVDS Driver Enable) that is located in
register SCU_CON. With LDEN = 0, all LVDS drivers are disabled and in power-down
mode. With LDEN = 1 all LVDS drivers are enabled for operation.
Table 10-29 LVDS Outputs of MSC0/MSC1
Signal/Pin
Short Name
Description
FCLP0A MSC0 differential driver clock output positive A
FCLN0 MSC0 differential driver clock output negative
SOP0A MSC0 differential driver serial data output positive A
SON0 MSC0 differential driver serial data output negative
FCLP1A MSC1 differential driver clock output positive A
FCLN1 MSC1 differential driver clock output negative
SOP1A MSC1 differential driver serial data output positive A
SON1 MSC1 differential driver serial data output negative
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