TC1796
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
User’s Manual 19-32 V2.0, 2007-07
ASC, V2.0
19.3.2.1 ASC0 Clock Control Register
The Clock Control Register ASC0_CLC allows the programmer to adapt the functionality
and power consumption of the ASC modules to the requirements of the application. The
description below shows the clock control register functionality which is implemented for
the ASC modules. Because ASC0 and ASC1 share one common clock control interface,
ASC0_CLC controls the f
ASC
module clock signal, sleep mode, suspend mode and fast
shut-off mode for both modules.
ASC0_CLC
ASC0 Clock Control Register (00
H
) Reset Value: 0000 0003
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
RMC 0
FS
OE
SB
WE
E
DIS
SP
EN
DIS
S
DIS
R
rw r rw w rw rw r rw
Field Bits Type Description
DISR 0rwModule Disable Request Bit
Used for enable/disable control of the module.
DISS 1rModule Disable Status Bit
Bit indicates the current status of the module.
SPEN 2rwModule Suspend Enable for OCDS
Used to enable the suspend mode.
EDIS 3rwSleep Mode Enable Control
Used to control module’s sleep mode.
SBWE 4wModule Suspend Bit Write Enable for OCDS
Determines whether SPEN and FSOE are write-
protected.
FSOE 5rwFast Switch Off Enable
Used to switch off fast clock in Suspend Mode.
RMC [15:8] rw 8-bit Clock Divider Value in RUN Mode
0 [7:6],
[31:16]
r Reserved
Read as 0; should be written with 0.
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