TC1796
Peripheral Units (Vol. 2 of 2)
Asynchronous/Synchronous Serial Interface (ASC)
User’s Manual 19-33 V2.0, 2007-07
ASC, V2.0
Note: After a hardware reset operation, the two ASC modules are disabled.
Note: The number of module clock cycles (wait states) which are required for a
“destructive read” access (means: flags/bits are set/cleared by one read access)
to ASC module register depends on the selected CLC clock frequency, which is
selected via bit field RMC in the CLC register. Therefore, increasing
ASC0_CLC.RMC may result in a longer SPB read cycle access time.
Note: Further details of the clock control register functionality are described in section
“Clock Control Register CLC” on Page 3-24 of the TC1796 User’s Manual
System Units part (Volume 1).
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