TC1796
System Units (Vol. 1 of 2)
System Control Unit
User’s Manual 5-8 V2.0, 2007-07
SCU, V2.0
5.2 Configuration Input Sampling
Several device pins of the TC1796 are latched either by a hardware reset or power-on
reset operation. The latched states of such pins may directly determine the start-up
configuration and conditions of the TC1796. The latched pins are divided into two types:
• Software configuration inputs, which are latched into a register and have no direct
influence on the device start-up configuration
• Hardware configuration inputs, which directly influence the start-up behavior of the
TC1796
Table 5-3 determines which pins are latched either by a hardware or power-on reset
operation. The state of the corresponding signals is always latched at the rising edges
of HDRST or PORST.
Table 5-3 Configuration Input Sampling
Configuration
Type
Reset Signal Pins Remark
Software
Configuration
HDRST P0.[15:0] The states of these pins are latched
in register SCU_SCLIR (see also
Section 10.3.3.2 on Page 10-24).
Hardware
Configuration
HDRST P10.[3:0]
(HWFCG[3:0])
The states of these pins are used for
selection of the Boot option (see
Table 4-3 on Page 4-12). Its state is
latched in bit field RST_SR.HWCFG.
PORST BRKIN The state of this pin is used for
selection of the Boot option and for
debug purposes.
P5.3/TXD1A The state of this pin determines
whether oscillator bypass mode is
selected or not (see also Table 3-1
on Page 3-9)
BYPASS The state of this pin determines
whether P5.3/TXD1A is evaluated or
not. Additionally, the latched state of
BYPASS controls the noise
suppression filters of pins PORST,
HDRST, and NMI.
TESTMODE The state of this pin is used for device
test mode selection. For normal
device operation, this pin should be
always be set to 1 level.
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