TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-51 V2.0, 2007-07
DMA, V2.0
12.2.2 General Control/Status Registers
The bits in the Channel Reset Request Register are used to reset DMA channel mx.
DMA_CHRSTR
DMA Channel Reset Request Register
(010
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
14131211109876543210
CH
17
CH
16
CH
15
CH
14
CH
13
CH
12
CH
11
CH
10
CH
07
CH
06
CH
05
CH
04
CH
03
CH
02
CH
01
CH
00
rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh
Field Bits Type Description
CH0x
(x = 0-7)
xrwhChannel 0x Reset
These bits force the DMA channel 0x to stop its current
DMA transaction. Once set by software, this bit will be
automatically cleared when the channel has been reset.
Writing a 0 to CH0x has no effect.
0
B
No action (write) or the requested channel reset
has been reset (read).
1
B
DMA channel 0x is stopped. More details see
Page 12-16.
CH1x
(x = 0-7)
8+x rwh Channel 1x Reset
These bits force the DMA channel 1x to stop its current
DMA transaction. Once set by software, this bit will be
automatically cleared when the channel has been reset.
Writing a 0 to CH1x has no effect.
0
B
No action (write) or the requested channel reset
has been reset (read).
1
B
DMA channel 1x is stopped. More details see
Page 12-16.
0 [31:16] r Reserved
Read as 0; should be written with 0.
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