TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-109 V2.0, 2007-07
DMA, V2.0
Note: The bit coding of the system interrupt service request control registers is identical
to that of the DMA service request control registers shown two pages before.
12.3.4 DMA Controller Address Map
The DMA controller register block address map is shown in Figure 12-33. It shows how
the different register blocks are arranged, and adds some absolute address information.
Figure 12-33 DMA Controller Register Block Address Map
0 [9:8], 11,
[31:16]
r Reserved
Read as 0; should be written with 0.
Field Bits Type Description
MCA05710
General Module Control
DMA
Control/Status Registers
F000 3C00
H
F000 3C10
H
F000 3C80
H
F000 3D80
H
F000 3C30
H
DMA Channel
00 - 07
Registers
F000 3E78
H
Move Engine Registers
DMA
Control/Status Registers
F000 3C54
H
DMA Channel
10 - 17
Registers
MLI Service Request
Control Registers
System Service Request
Control Registers
DMA Service Request
Control Registers
F000 3E8C
H
F000 3EA0
H
F000 3EE0
H
F000 3EFC
H
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