TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-65 V2.0, 2007-07
EBU, V2.0
13.9 Burst Mode Read Accesses
Synchronous burst read accesses of the EBU support the following features:
• Fully synchronous timing with flexible programmable timing parameters
(address cycles, read wait cycles, data cycles)
• Simultaneous support for two different Burst Flash Types
• Programmable WAIT operation
• Programmable Burst Mode and burst length
• 16-bit or 32-bit data bus width
• Re-synchronization of read data to a feedback clock to maximize the frequency of
operation
When it is necessary to perform non-burst accesses to Burst Flash devices, it is
necessary to reprogram the characteristics of the corresponding chip select region for
the appropriate asynchronous access.
13.9.1 Signal List
The following signals of the EBU are used for the burst read accesses:
Table 13-18 Burst Flash Mode Signal List
Signal Type Function
D[31:0] I Data bus lines 0-31
A[23:0] O Address bus outputs 0-23
ADV O Address valid strobe output
CS[3:0] O Chip select outputs 0-3
RD O Read control output
BAA O Burst address advance control output
WAIT I Wait/terminate burst control input
BFCLKO O Burst Flash clock output
BFCLKI I Burst Flash clock input (feedback)
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