Infineon Technologies TC1796 User Manual

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-58 V2.0, 2007-07
MLI, V2.0
23.2.5.1 Parity/Time-out Error Event
A parity/time-out error event is generated when a programmable maximum number of
parity errors or a programmable maximum number of Non-Acknowledge errors have
been reached. Both events have separate status/control bits but are concatenated to
one common error event.
Figure 23-39 Parity/Time-out Error Event Logic
23.2.5.2 Normal Frame Sent x Event
A Normal Frame sent in pipe x (x = 0-3) event is generated when a Normal Frame has
been sent and correctly received in pipe x.
Figure 23-40 Normal Frame Sent in Pipe x Event Logic
PEIE
TIER
PEIR
MCA05896_mod
Parity/
Time- out
Error
Event
TEIE
TIER
TEIR
Software
Clear
Software
Clear
PEI
TISR
Set
TEI
TISR
Set
Parity
Error
Event
Time-out
Error
Event
3
To SR0
To SR1
To SR6
To SR7
.
.
.
.
.
.
PTEI P
TINPR
≥ 1
NFSIEx
TIER
NFSIRx
Software
Clear
MCA05897_mod
x = 0-3
Normal Frame
Sent in Pipe x
Event
NFSIx
TISR
Set
3
To SR0
To SR1
To SR6
To SR7
.
.
.
.
.
.
NFSIPx
TINPR

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English