TC1796
System Units (Vol. 1 of 2)
Introduction
User’s Manual 1-30 V2.0, 2007-07
Intro, V2.0
1.3.3 Analog-to-Digital Converters
The TC1796 contains two medium-speed Analog-to-Digital Converters (ADC0 and
ADC1) with identical functionality and a third fast Analog-to-Digital Converter (FADC).
ADC0 and ADC1 provide 2-3 µs conversion time @ 10-bit resolution and are intended
mainly for single-ended signals. They offer a very flexible and comprehensive control for
monitoring a large number of relatively slow signals, including synchronous conversion
of both ADCs.
The FADC offers very fast conversion rates (280 ns @ 10-bit resolution) thus allowing
sampling of high-frequency signals. For slow and mid-range frequency signal heavy
oversampling can be performed and thus expensive filters can be avoided.
1.3.3.1 Analog-to-Digital Converters (ADC0 and ADC1)
The two on-chip ADC modules of the TC1796 are analog-to-digital converters with 8-bit,
10-bit, or 12-bit resolution including sample & hold functionality. The A/D converters
operate by the method of successive approximation. A multiplexer selects up to
32 analog inputs that can be connected to the 16 conversion channels in each ADC
module. An automatic self-calibration adjusts the ADC modules to changing
temperatures or process variations.
Features
• 8-bit, 10-bit, 12-bit A/D conversion
• Conversion time below 2.5 µs @ 10-bit resolution
• Extended channel status information on request source
• Successive approximation conversion method
• Total Unadjusted Error (TUE) of ±2 LSB @ 10-bit resolution
• Integrated sample & hold functionality
• Direct control of up to 16(32) analog input channels per ADC
• Dedicated control and status registers for each analog channel
• Powerful conversion request sources
• Selectable reference voltages for each channel
• Programmable sample and conversion timing schemes
• Limit checking
• Flexible ADC module service request control unit
• Synchronization of the two on-chip A/D Converters
• Automatic control of external analog multiplexers
• Equidistant samples initiated by timer
• External trigger and gating inputs for conversion requests
• Power reduction and clock control feature
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