TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-79 V2.0, 2007-07
GPTA, V2.0
24.2.3.4 Local Timer Cell LTC63
Registers
The following registers are assigned to Local Timer Cell LTC63:
• LTCCTR63 = Local Timer Cell Control Register 63 (see Page 24-188)
• LTCXR63 = Local Timer Cell X Register 63 (see Page 24-190)
• SRSC3 = Service Request State Clear Register 3 (see Page 24-213)
• SRSS3 = Service Request State Set Register 3 (see Page 24-214)
Features
The GPTA Local Timer Cell array has one special cell, LTC63, which provides the
following special features:
• Compare Mode on greater equal compare of the last timer, 16-bit based with
following actions:
– Service request generation
– Output signal transition generation (set, reset, toggle the output signal).
• Bit Reversal Mode:
– Timer can be selected to enable a special PWM Mode, called pulse count
modulation (PCM)
• Compare Value Switching can be triggered by a hardware signal. This function can
generate a service request. One Shot Mode makes it possible to stop the function
after the first event.
Architecture
LTC63 is locally equipped with a 16-bit compare register, a 16-bit shadow register and
a 16-bit greater comparator (Figure 24-54).
The LTC63 has the following inputs:
• A local input data bus (YI) carrying the local timer value of the adjacent LTC with
lower order number
• A TI input reporting the occurrence of a local timer value update of the adjacent LTC
with lower order number
• A trigger/enable input LTCkIN for compare value switching hooked to one of the
following signals sources:
– External port lines
– GTC00 to GTC31 outputs
– Clock bus signals
– PDL0 or PDL1 outputs
– Internal GPTA kernel input signals INTx (x = 0-3)
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