TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-42 V2.0, 2007-07
MLI, V2.0
23.2.2 General MLI Features
The general MLI features comprise the:
• Parity generation and checking (see Page 23-42)
• Non-Acknowledge error (see Page 23-45)
• Address prediction (see Page 23-45)
• Automatic data transfers (see Page 23-46)
• Access protection (see Page 23-47)
• Transmit priority (see Page 23-48)
• Transmission delay (see Page 23-48)
23.2.2.1 Parity Check and Parity Error Indication
For parity generation, the number of transmitted bits with the value of 1 is counted over
the header and the complete data field of a frame. For even parity, the parity bit is set if
the result of a modulo-2 division of the elaborated number is 1. For odd parity, the parity
bit is set if the result of a modulo-2 division of the elaborated number is 0.
For a parity error-free MLI connection, even parity must be selected in the transmitter
because the receiver operates only with even parity detection. The capability to select
odd parity can be used by the transmitter to force a parity error reply from the receiver
during the startup procedure of the MLI connection. This can be used to measure the
propagation delay and to optimize the ready delay time (see Page 23-71).
Note: There is no protection against frames where more than one bit is corrupted (e.g.
shortened frames). In such a case, an unpredicted behavior of the MLI module
may occur.
Transmitting Controller
The MLI transmitter counts the detected parity error conditions and generates a parity
error event if a programmable number (max. 16) of parity error conditions has occurred.
A parity error condition is indicated to the transmitter by the receiver after the
transmission of a frame (see Page 23-23). The transmitter parity error condition is
detected when the TREADY signal is sampled at low level within a programmable
number (TCR.MDP = maximum delay for parity errors) of TCLK clock cycles after
TVALID has been de-asserted to low.
If a transmitter parity error condition is detected, the MLI transmitter sets the parity error
flag TSTATR.PE and also decreases the maximum parity error counter TCR.MPE by 1.
The maximum parity error counter of the transmitter TCR.MPE determines the number
of transmit parity error conditions that can be still detected until a transmitter parity error
event is generated. If a transmitter parity error condition is detected and TCR.MPE is
becoming 0 or while it is 0, a transmitter parity error event is generated by setting bit
TISR.PEI (see Figure 23-39 on Page 23-58) and an SRx output line is activated if
enabled by TIER.PEIE = 1. After a transmitter parity error event occurred, TCR.MPE can
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