TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-125 V2.0, 2007-07
PCP, V2.0
11.14 Implementation of the PCP in the TC1796
The addresses of the PCP registers and memories in the TC1796 are given in the
following subsections.
11.14.1 PCP Memories
In the TC1796, the location of the registers and the memories sizes of the PRAM and the
CMEM are given in Table 11-16.
Note: “BE” means that in case of an access to this address region, a bus error is
generated.
Note: The complete address map of the PCP is described in Table 18-25 on Page 18-77
of this TC1796 System Units (Vol. 1 of 2) User’s Manual.
11.14.2 Parity Protection for PCP Memories
In the TC1796, the PRAM and CMEM memory blocks of the PCP are both equipped with
a parity error detection logic that makes it possible to detect parity errors separately for
PRAM or CMEM. In case of a parity error a NMI is generated.
Note that before using parity protection for PRAM and CMEM the first time after a power-
on reset operation (before setting the corresponding parity error enable bits), the
corresponding PCP memories must be completely initialized by a user program that
writes every memory location of it once.
Table 11-16 General Block Address Map
Unit Address
Range
Access Mode Size
Read Write
PCP Reserved F004 0000
H
-
F004 3EFF
H
BE BE –
PCP Registers F004 3F00
H
-
F004 3FFF
H
see
Page 11-52
256 bytes
Reserved F004 4000
H
-
F004 FFFF
H
BE BE –
PCP Data Memory (PRAM) F005 0000
H
-
F005 3FFF
H
nE, 32 nE, 32 16 Kbyte
Reserved F005 4000
H
-
F005 FFFF
H
BE BE –
PCP Code Memory (CMEM) F006 0000
H
-
F006 7FFF
H
nE, 32 nE, 32 32 Kbyte
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