Infineon Technologies TC1796 - 10.12.3.6 Port 9 Pad Driver Mode Register and Pad Classes

TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-80 V2.0, 2007-07
Ports, V2.0
10.12.3.6 Port 9 Pad Driver Mode Register and Pad Classes
The Port 9 pad driver mode register contains three bit fields that determine the pad driver
mode (output driver strength and slew rate) of Port 9 lines. The Port 9 port lines are all
class A2 pads (see also Figure 10-13).
P9_PDR
Port 9 Pad Driver Mode Register (40
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 PDMSC1 0 PDMSC0
rrwrrw
1514131211109876543210
0PD0
rrw
Field Bits Type Description
PD0 [2:0] rw Pad Driver Mode for MSC1/GPIO P9.8
(Class A2 pads; for coding see Page 10-11)
PDMSC0 [18:16] rw Pad Driver Mode for GPTA/MSC0 Outputs P9.[7:4]
(Class A2 pads; for coding see Page 10-11)
PDMSC1 [22:20] rw Pad Driver Mode for GPTA/MSC1 Outputs P9.[3:0]
(Class A2 pads; for coding see Page 10-11)
0 [15:3],
19,
[31:23]
r Reserved
Read as 0; should be written with 0.