TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-107 V2.0, 2007-07
DMA, V2.0
12.3.3.3 MLI Service Request Control Registers
The Service Request Control Registers of the MLI modules are located inside the DMA
address area, because the MLI modules do not have own FPI Bus interfaces. They
share one FPI Bus interface with the DMA controller.
The MLI0 module has eight interrupt output lines. Only four of them [3:0] are controlled
by the MLI0 service request registers. The MLI1 module has also eight interrupt output
lines, but only two of them [1:0] are controlled by to the MLI1 service request registers.
Note: The bit coding of the MLI0/MLI1 service request registers is identical to that of the
DMA Service Request Control Registers shown on the previous page.
DMA_MLI0SRCx (x = 0-3)
DMA MLI0 Service Request Control Register x
(2AC
H
-x*4
H
) Reset Value: 0000 0000
H
DMA_MLI1SRCx (x = 0-1)
DMA MLI1 Service Request Control Register x
(2BC
H
-x*4
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
SET
R
CLR
R
SRR SRE 0 TOS 0 SRPN
w w rh rw r rw r rw
Field Bits Type Description
SRPN [7:0] rw Service Request Priority Number
TOS 10 rw Type of Service Control
SRE 12 rw Service Request Enable
SRR 13 rh Service Request Flag
CLRR 14 w Request Clear Bit
SETR 15 w Request Set Bit
0 [9:8], 11,
[31:16]
r Reserved
Read as 0; should be written with 0.
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