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Infineon Technologies TC1796 User Manual

Infineon Technologies TC1796
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TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-19 V2.0, 2007-07
FADC, V2.0
26.1.6.3 Filter Concatenation
As shown in Figure 26-6, it is possible to concatenate the two filters by using the result
value of filter 0 as input value for filter 1. Figure 26-9 shows an example for the filter
concatenation.
Filter 0 operates with following parameters:
Intermediate results are calculated from four filter input values (conversion results)
A final result is calculated by four intermediate results
Filter 1 operates with following parameters:
Concatenation enabled (FCR1.INSEL = 010
B
)
Intermediate results are calculated from three filter 1 input values
A final result is calculated by two intermediate results
Figure 26-9 Filter Concatenation Example
Filter 0 operates with the same parameters as in the example shown in Figure 26-8. A
Filter 1 input value is given by each final result of filter 0. Filter 1 can store only one
intermediate result in its IRR11 register.
MCT06046
Time
FR0
Filter 0
FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11
v
FR12
v
FR13
v
FR14
FRR1
0+IR10+0 IR1+IR2 IR2+IR3 IR3+IR4
Filter 1
Initial Start of
Filter Algorithm
IRR11
IR10 IR2 IR3 IR4
0
CRR1
FR0
FR0+FR1
0
FR3
FR3+FR4
0
FR6
FR6+FR7
0
FR9
FR9+FR10
0
FR12
FR12+FR13
CC C C C
Intermediate Result
Calculation in Filter 0
Intermediate Result
Calculation in Filter 1
FRR1 = Content of the final result register 1.
IRR1 = Content of intermediate result register 11.
C = Calculation of intermediate and final results in Filter 1.
FRk = Final results of Filter 0, numbered by k.
CRR1= Content of Filter 1 current result register 1.
IRk = Intermediate results in Filter 1, numbered by k.
Filter Parameters:
FCR0.ADDL = 011
B
FCR0.MAVL = 11
B
FCR1.ADDL = 010
B
FCR1.MAVL = 01
B

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Infineon Technologies TC1796 Specifications

General IconGeneral
BrandInfineon Technologies
ModelTC1796
CategoryController
LanguageEnglish