TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-18 V2.0, 2007-07
FADC, V2.0
a filter sequence and after each intermediate result storage. CRRn.AC is
decremented after each conversion result addition and indicates how many additions
are still to be executed until the next intermediate result is stored. Values for one up
to eight conversions can be selected for FCRn.ADDL.
• FCRn.MAVL:
This parameter determines the number of intermediate result registers that are used
for a final result calculation. FCRn.MAVL is loaded into CRRn.MAVS at the start of a
filter sequence. Values for none up to three intermediate result registers can be
selected for FCRn.MAVL.
Initial State
In order to start a filter algorithm for filter block n, the following actions must be executed:
1. Program bit field FCRn.ADDL with FCRn.INSEL = 000
B
(filter disabled)
2. Select filter n input source and operation by writing FCRn.INSEL with the appropriate
value
3. Reset filter block n by writing GCR.RSTFn = 1
4. Start a continuous conversion
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