TC1796
System Units (Vol. 1 of 2)
Memory Maps
User’s Manual 9-4 V2.0, 2007-07
MemMaps, V2.0
9.2 Contents of the Segments
This section summarizes the contents of the segments.
Segments 0-7
These segments are reserved segments in the TC1796.
Segment 8
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment allows
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM) and the
external EBU space.
From the CPU point of view (PMI and DMI), this memory segment allows cached
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM) and the
external EBU space.
Segment 9
This memory segment is reserved in the TC1796.
Segment 10
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment allows
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM) and the
external EBU space.
From the CPU point of view (PMI and DMI), this memory segment allows non-cached
accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM) and the
external EBU space.
Segment 11
This memory segment is reserved in the TC1796 (comparable to segment 9).
Segment 12
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment is
reserved in the TC1796.
From the PLMB point of view (PMI), this memory segment is reserved in the TC1796.
From the DLMB point of view (DMI), this memory segment allows cached accesses to
all DMU memories (SRAM and SBRAM).
Segment 13
From the SPB point of view (PCP, DMA, and Cerberus), this memory segment allows
accesses to the external peripheral and emulator space.
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