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Infineon Technologies TC1796 User Manual

Infineon Technologies TC1796
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TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-2 V2.0, 2007-07
SSC, V2.1
20.1.1 Overview
The SSC supports full-duplex and half-duplex serial synchronous communication up to
37.5 Mbit/s (@ 75 MHz module clock) with Receive and Transmit FIFO support. The
serial clock signal can be generated by the SSC itself (Master Mode) or can be received
from an external master (Slave Mode). Data width, shift direction, clock polarity and
phase are programmable. This allows communication with SPI-compatible devices.
Transmission and reception of data is double-buffered. A shift clock generator provides
the SSC with a separate serial clock signal. Seven slave select inputs are available for
Slave Mode operation. Eight programmable slave select outputs (chip selects) are
supported in Master Mode.
Note: The SSC0 contains an 8-stage Receive and Transmit FIFO. The SSC1 does not
provide any FIFO functionality. Therefore, all FIFO related references in
Section 20.1 and Section 20.2 are not valid for the SSC1 module!
Features
Master and Slave Mode operation
Full-duplex or half-duplex operation
Automatic pad control possible
Flexible data format
Programmable number of data bits: 2 to 16 bits
Programmable shift direction: LSB or MSB shift first
Programmable clock polarity: Idle low or idle high state for the shift clock
Programmable clock/data phase: Data shift with leading or trailing edge of the shift
clock
Baud rate generation from 37.5 Mbit/s to 572.2 bit/s (@ 75 MHz module clock)
Interrupt generation
On a transmitter empty condition
On a receiver full condition
On an error condition (receive, phase, baud rate, transmit error)
Flexible SSC pin configuration
Seven slave select inputs SLSI[7:1] in Slave Mode
Eight programmable slave select outputs SLSO[7:0] in Master Mode
Automatic SLSO generation with programmable timing
Programmable active level and enable control
SSC0 only: 8-stage Receive FIFO (RXFIFO) and 8-stage Transmit FIFO (TXFIFO)
Independent control of RXFIFO and TXFIFO
2- to 16-bit FIFO data width
Programmable receive/transmit interrupt trigger level
Receive and Transmit FIFO filling level indication
Overrun error generation
Underflow error generation

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Infineon Technologies TC1796 Specifications

General IconGeneral
BrandInfineon Technologies
ModelTC1796
CategoryController
LanguageEnglish