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Infineon Technologies TC1796 - 11.11.29 PRAM Bit Operations

Infineon Technologies TC1796
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TC1796
System Units (Vol. 1 of 2)
Peripheral Control Processor (PCP)
User’s Manual 11-99 V2.0, 2007-07
PCP, V2.0
11.11.29 PRAM Bit Operations
This section describes the MCLR and MSET instructions of the PCP.
Note: MCLR and MSET are read/modify/write operations that cannot be interrupted by
an access from another FPI master. They can be used to implement semaphore
systems.
MCLR Syntax MCLR.PI Ra, [#offset6]
Description Perform an ‘AND’ of the contents of the specified register with
the contents of the PRAM location specified by the addition of
contents of the PRAM Data Pointer, shifted left by six bits,
and the zero-extended 6-bit value offset. Write the result back
to the PRAM location.
Operation R[a] = R[a].AND.PRAM[DPTR<<6+#offset6]
PRAM[DPTR<<6+#offset6] = R[a]
Flags N, Z
MSET Syntax MSET.PI Ra, [#offset6]
Description Perform an ‘OR’ of the contents of the specified register with
the contents of the PRAM location specified by the addition of
contents of the PRAM Data Pointer, shifted left by six bits,
and the zero-extended 6-bit value offset. Write the result back
to the PRAM location.
Operation R[a] = R[a].OR.PRAM[DPTR<<6+#offset6]
PRAM[DPTR<<6+#offset6] = R[a]
Flags N, Z

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