TC1796
System Units (Vol. 1 of 2)
CPU Subsystem
User’s Manual 2-9 V2.0, 2007-07
CPU, V2.0
2.4 TC1796 CPU Subsystem Registers
This section only describes the implementation-specific features of the registers listed in
Table 2-1. For complete descriptions of all registers, please refer to the TriCore 1
Architecture Manual.
TC1796 implementation-specific CPU registers are referred directly in this section.
The complete and detailed address map of the CPU and processor subsystem registers
shown in Table 2-1 above is located in Chapter 18. The entries in column “Address
Map” of Table 2-1 directly point to the corresponding pages.
Table 2-1 CPU and Processor Subsystem Registers
Registers Purpose Description Address Map
Core Special
Function Registers
(CSFRs)
Program state information,
context and stack management,
interrupt and trap control,
system control
Architecture
Manual
see
Page 18-108
CPU Slave Interface
Registers (CPSs)
Software break control and
software service request control
see
Page 18-104
Core General
Purpose Registers
(GPRs)
Address and data see
Page 18-105
Core Debug
Registers (OCDS)
Debug control see
Page 18-108
Memory Protection
Registers
Memory protection control and
mode selection
see
Page 18-105
Program Memory
Interface Registers
(PMI)
PMI instruction cache control and
status
see
Page 2-26
see
Page 18-124
Data Memory
Interface Registers
(DMI)
DMI status and trap flags see
Page 2-34
see
Page 18-123
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