Infineon Technologies TC1796 - Page 1112

TC1796
System Units (Vol. 1 of 2)
Register Overview
User’s Manual 18-123 V2.0, 2007-07
Regs, V2.0
Table 18-39 Address Map of DMI
Short Name Description Address Access Mode Reset Value
Read Write
DMI Registers
– Reserved F87F FC00
H
-
F87F FC04
H
nBE nBE –
DMI_ID DMI Module
Identification Register
F87F FC08
H
U, SV
1)
0008 C0XX
H
– Reserved F87F FC0C
H
nBE nBE –
DMI_CON DMI Control Register F87F FC10
H
U, SV SV, E 0000 0070
H
– Reserved F87F FC14
H
nBE nBE –
DMI_STR DMI Synchronous Trap
Flag Register
F87F FC18
H
U, SV
1)2)
1)
0000 0000
H
– Reserved F87F FC1C
H
nBE nBE –
DMI_ATR DMI Asynchronous Trap
Flag Register
F87F FC20
H
U, SV
1)2)
1)
0000 0000
H
– Reserved F87F FC24
H
nBE nBE –
DMI_CON1 DMI Control Register 1 F87F FC28
H
U, SV,
32
SV,
E, 32
0000 0000
H
– Reserved F87F FC2C
H
-
F87F FCFC
H
nBE nBE –
1) Access to the DMI registers must only be made with double-word-aligned word accesses. An access not
conforming to this rule, or an access that does not follow the specified privilege mode (supervisor mode,
Endinit-protection), or a write access to a read-only register, will be lead to a bus error if the access was from
the FPI Bus, or to a trap, flagged with a DMI Control Register Error Flag (see DMI_STR/DMI_ATR registers)
in case of a CPU load/store access.XXX
2) Reading this register in supervisor mode returns the contents and then clears the register. Reading it in user
mode only returns the contents of the register; it is not cleared. No error will be reported in this case.