TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual 3-6 V2.0, 2007-07
Clock, V2.0
3.2.1.2 Oscillator Run Detection
The oscillator run detection logic indicates during oscillator start-up after a power-on
operation whether the oscillator is already running or if an emergency operation with PLL
base frequency has to be started. When the oscillator run condition is met, bit
OSC_CON.OSCR is set and the output clock f
OSC
is enabled to supply the clock signal
to the rest of the system. Figure 3-4 shows the oscillator run detection logic.
Figure 3-4 Oscillator Run Detection Circuitry
The oscillator run detection consists of two counters, Counter A and B. The 3-bit Counter
A is running with the oscillator frequency and stops at its terminal count value. The 5-bit
Counter B is running at f
N
, the divided (N-Divider) VCO clock frequency. Always at the
terminal count of Counter B the state of Counter A is latched in a flip-flop, bit OSCR is
updated, and both counters a reset. This means, if Counter A does not reaches its
terminal count value (8 f
OSC
clock periods) within a counter period of Counter B (32 f
N
clock periods), the oscillator is designated as “not running” by OSCR = 0. If Counter A is
at its terminal count value at the end of the counter period of Counter B, the “running”
state (OSCR = 1) is detected.
The circuit can start without a reset and becomes defined after at least 32 pulses of
counter B. Setting bit OSC_CON.ORDRES makes it possible to start the oscillator run
detection during normal operation of the TC1796, e.g. in case of a PLL loss-of-lock
condition.
MCA05602
Main
Oscillator
(4 - 25 MHz)
PLL
(4 - 8 MHz)
OSC_CON
ORDRES
OSC_CON
OSCR
f
OSC
f
N
Counter A
(3-Bit)
R
Q
Counter B
(5-Bit)
R
Q
D Q
≥1
≥1
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