TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-234 V2.0, 2007-07
GPTA, V2.0
24.5.1 Bit Protection
Bits with bit protection (this is valid, for example, for all bits in the Service Request State
Registers) are not changed during a read-modify-write instruction, that is when hardware
sets a request state bit between the read and the write of the read-modify-write
sequence. For bit protected bits it is guaranteed that a hardware setting operation always
has priority. Thus, no hardware triggered events are lost.
24.5.2 Service Request Registers
See “SRSC2” on Page 24-211.
24.5.3 Local Timer Cell Registers
See “LTCCTRk (k = 00-62)” on Page 24-180.
LTCXRk Local Timer Cell X Register k
(k = 00-62)
200
H
+
k × 8 + 4
Page 24-190
LTCCTR63 Local Timer Cell Control Register 63 3F8
H
Page 24-188
LTCXR63 Local Timer Cell X Register 63 3FC
H
Page 24-190
OMCRLg Output Multiplexer Control Register for
Lower Half of Group g (g = 0-4, 7-13)
not directly
addressable
see
Page 24-229
Page 24-239
OMCRLg Output Multiplexer Control Register for
Upper Half of Group g (g = 0-4, 7-13)
Page 24-241
LIMCRLg Input Multiplexer Control Register for
Lower Half of LTC Group g (g = 0-7)
Page 24-243
LIMCRLg Input Multiplexer Control Register for
Upper Half of LTC Group g (g = 0-7)
Page 24-245
Table 24-23 LTCA2 Kernel Registers (cont’d)
Register
Short Name
Register Long Name Offset
Address
Description
see
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