TC1796
System Units (Vol. 1 of 2)
System Control Unit
User’s Manual 5-36 V2.0, 2007-07
SCU, V2.0
The FPU interrupt uses the system interrupt node DMA_SYSSRC0 located in the DMA
controller. A description of this register can be found on Page 12-108. Note that
DMA_SYSSRC0.TOS should be written with 00
B
because FPU interrupt should only be
serviced by the CPU (and not by the PCP).
5.4.2 Flash Interrupt
The flash module can generate an interrupt when the following conditions occur:
• End-of-busy state
• Protection error
• Sequence error
• Single-bit ECC error
Each source can be individually enabled and disabled. The detailed description of the
flash interrupt generation can be found at “Flash Interrupt Generation and Control”
on Page 7-36. The Flash interrupt uses the system interrupt node DMA_SYSSRC1
located in the DMA module.
5.4.3 External Interrupts
As shown in Figure 5-5 on Page 5-15, the External Request Unit provides two interrupt
sources for events on external pins. The interrupt events can be defined by programming
the corresponding registers in the ERU.
The two ERU interrupts are controlled by the system interrupt nodes DMA_SYSSRC2
and DMA_SYSSRC3 located in the DMA module. A description of this register can be
found on Page 12-108.
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