TC1796
System Units (Vol. 1 of 2)
Program Memory Unit
User’s Manual 7-51 V2.0, 2007-07
PMU, V2.0
7.2.11.3 Margin Control Registers
The Margin Control Registers for Program Flash (MARP) and for Data Flash (MARD) are
defined as follows:
FLASH_MARP
Flash Margin Control Register PFLASH
(1018
H
) Reset Value: 0000 8000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
TR
AP
DIS
0
MARGIN
1
MARGIN
0
rw r rw rw
Field Bits Type Description
MARGIN0 [1:0] rw PFLASH Margin Selection for Low Level
00
B
Standard margin selected
01
B
High margin for 0 (low) level selected
10
B
Reserved
11
B
Reserved
MARGIN1 [3:2] rw PFLASH Margin Selection for High Level
00
B
Standard margin selected
01
B
High margin for 1 (high) level selected
10
B
Reserved
11
B
Reserved
TRAPDIS 15 rw PFLASH Double-Bit Error LMB Bus Error Disable
0
B
If a double-bit error occurs in PFLASH, a bus
error at PLMB or DLMB is generated.
1
B
If a double-bit error occurs in PFLASH, no LMB
bus error is generated.
After Boot ROM exit, double-bit error traps are enabled
(TRAPDIS = 0).
0 [14:4],
[31:16]
r Reserved
Read as 0; should be written with 0.
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