Infineon Technologies TC1796 - Page 403

TC1796
System Units (Vol. 1 of 2)
Program Memory Unit
User’s Manual 7-52 V2.0, 2007-07
PMU, V2.0
FLASH_MARD
Flash Margin Control Register DFLASH
(101C
H
) Reset Value: 0000 8000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
TR
AP
DIS
0
BNK
SEL
MARGIN
1
MARGIN
0
rw r rw rw rw
Field Bits Type Description
MARGIN0 [1:0] rw DFLASH Margin Selection for Low Level
00
B
Standard margin selected
01
B
High margin for 0 (low) level selected
10
B
Reserved
11
B
Reserved
MARGIN1 [3:2] rw DFLASH Margin Selection for High Level
00
B
Standard margin selected
01
B
High margin for 1 (high) level selected
10
B
Reserved
11
B
Reserved
BNKSEL 4rwDFLASH Bank Selection
0
B
DFLASH bank 0 selected for margin control
1
B
DFLASH bank 1 selected for margin control
TRAPDIS 15 rw DFLASH Double-Bit Error DLMB Bus Error Disable
0
B
If a double-bit error occurs in DFLASH, a DLMB
bus error is generated.
1
B
If a double-bit error occurs in DFLASH, no
DLMB bus error is generated.
After Boot ROM exit, double-bit error traps are enabled
(TRAPDIS = 0).
0 [14:5],
[31:16]
r Reserved
Read as 0; should be written with 0.