TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-35 V2.0, 2007-07
MSC, V2.0
21.1.5.5 Interrupt Request Compressor
The interrupt control logic of the MSC uses an interrupt compressing scheme that allows
high flexibility in interrupt processing. Each of the four interrupt sources can be directed
via a 2-bit interrupt node pointer to one of the four service request outputs SR[3:0]. This
also makes it possible to connect more than one interrupt source to one interrupt output
SRx.
Figure 21-27 MSC Interrupt Request Compressor
Note: The number of available MSC interrupt outputs depends on the implementation of
the MSC module(s) in the specific product (see Section for TC1796 details).
MCA05821
EDIP
ICR
ECIP
ICR
TFIP
ICR
RDIP
ICR
Service
Request
Output
SR0
Service
Request
Output
SR1
Service
Request
Output
SR2
Service
Request
Output
SR3
ECI
TFI
RDI
EDI
01
10
11
00
01
10
11
00
01
10
11
00
≥1
≥1
≥1
≥1
2
2
2
2
01
10
11
00
Data Frame
Interrupt
Command
Frame
Interrupt
Time Frame
Interrupt
Receive Data
Interrupt
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