Infineon Technologies TC1796 - 22.9.4.4 Pad Output Driver Register

TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-208 V2.0, 2007-07
MultiCAN, V2.0
22.9.4.4 Pad Output Driver Register
The Port 6 pad driver mode register contains bit fields that determine the output driver
strength and the slew rate of MultiCAN output lines. The coding of the PDx bit field
combinations is shown in Table 22-19.
PDx Selection Table
P6_PDR
Port 6 Pad Driver Mode Register (40
H
) Reset Value: 0000 0000
H
31 30 28 27 26 24 23 22 20 19 18 16 15 0
0
PD
CAN23
0
PD
CAN01
0
PD
SSC1
0 0 0
rrwrrwr rw r rw r
Field Bits Type Description
PDCAN01 [26.24] rw Pad Driver Mode for P6.9/TXDCAN0 and
P6.11/TXDCAN1
1)
1) Coding of bit field see Table 22-19. Shaded bits and bit fields are “don’t care” for CAN I/O port control.
PDCAN23 [30:28] rw Pad Driver Mode for P6.13/TXDCAN2 and
P6.15
1)
/TXDCAN3
Table 22-19 Pad Driver Mode Mode Selection (Class A2 Pads)
PDx Bit Field Driver Strength Signal Transitions
000
B
Strong driver Sharp edge
1)
1) In strong driver mode, the output driver characteristics of class A2 pads can be additionally controlled by the
temperature compensation logic.
001
B
Medium edge
1)
010
B
Soft edge
1)
011
B
Weak driver –
100
B
Medium driver Sharp edge
101
B
Medium edge
110
B
Soft edge
111
B
Weak driver –