TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual 3-1 V2.0, 2007-07
Clock, V2.0
3 Clock System and Control
3.1 Overview
This chapter describes the TC1796 clock system. Topics covered include clock gating,
clock domains, clock generation, the operation of clock circuitry, boot-time operation,
fail-safe operation, and clock control registers.
The TC1796 clock system performs the following functions:
• Acquires and buffers incoming clock signals to create a master clock frequency
• Distributes in-phase synchronized clock signals throughout the TC1796’s entire clock
tree
• Divides a system master clock frequency into lower frequencies required by the
different modules for operation
• Dynamically reduces power consumption during operation of functional units
• Statically reduces power consumption through programmable power-saving modes
• Reduces electromagnetic interference (EMI) by switching off unused modules
The clock system must be operational before the TC1796 can function, so it contains
special logic to handle power-up and reset operations. Its services are fundamental to
the operation of the entire system, so it contains special fail-safe logic.
Figure 3-1 shows the structure of the TC1796 clock system. The system clock f
SYS
is
generated by the oscillator circuit and the PLL (phase-locked loop) unit. Each peripheral
module operates with its module clocks f
CLC
and f
MOD
. Suffix “MOD” is a place holder for
the module name, e.g. f
ASC0
.
The functionality of the control blocks shown in Figure 3-1 varies depending on the
functional unit being controlled. Some functional units such as the watchdog timer, are
directly driven by the system clock. The implemented clock control register options are
described for each unit on Table 3-9 on Page 3-39.
All clock control registers CLC and the fractional divider registers FDR are Endinit-
protected.
Features of the TC1796 Clock System
• PLL operation for multiplying clock source by different factors
• Direct drive capability for direct clocking
• Comfortable state machine for secure switching between basic PLL, direct or
prescaler operation
• Sleep and Power-Down Mode support
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