TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-10 V2.0, 2007-07
GPTA, V2.0
24.2.2.1 Filter and Prescaler Cell (FPC)
Each GPTA contains six filter and prescaler cells, FPC0 to FPC5. As shown in
Figure 24-4, each FPC is equipped with an signal input multiplexer, a clock multiplexer,
an edge detection unit, a 16-bit timer, a 16-bit compare register, a 16-bit comparator, and
an FPC control unit (see also Page 24-115 for the FPC functional algorithm description).
Figure 24-4 Filter and Prescaler Cell Architecture
FPC Registers
The following registers are assigned to the filter and prescaler cells FPCk (k = 0-5):
• FPCSTAT = Filter and Prescaler Cell Status Register (see Page 24-155)
• FPCCTRk = Filter and Prescaler Cell Control Register k (see Page 24-156)
• FPCTIMk = Filter and Prescaler Cell Timer Register k (see Page 24-158)
≥
MCA05913
IPS
FPCCTRk
SINk0
SINk4 =
f
GPTA
SINk5 = SOLk-1
CLK
CINk1
CINk3
CINk2
Edge
Detect
SINk1
SINk2
SINk3
Pin
Select
Clock
Select
FE
RE
FPC
Control
Logic
CMP
f
GPTA
FPCCTRk
Compare Value
TIM
FPCTIMk
Timer
SOTk
SOLk
2
MOD
REGk
FPCSTAT
FEGk
FPCSTAT
CINk0 =
f
GPTA
RTG
FPCCTRk
FPC
SIN
CIN
3
16 16
3
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