TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-247 V2.0, 2007-07
GPTA, V2.0
24.6 GPTA Module Implementation
This section describes the GPTA interfaces as implemented in TC1796 with the clock
control, port and Micro Second Channel connections, interrupt control, and address
decoding.
24.6.1 Interconnections of the GPTA0/GPTA1/LTCA2 Modules
The following items are described in this section:
• GPTA module (kernel) external registers
• Port control and connections
– I/O port line assignment
– I/O function selection
– Pad driver characteristics selection
– Emergency control of GPTA outputs
• On-chip connections
– Clock bus connections
– MSC controller connections
– FADC connections
– MultiCAN, SCU, and DMA connections
– SCU connections (ADC, DMA)
• Module clock generation
• Interrupt registers
• GPTA address map
Figure 24-86 shows the TC1796 specific implementation details and interconnections of
the modules GPTA0, GPTA1 and LTCA2. The modules are supplied by clock control and
address decoding logic.
Each GPTA0/1 module has 56 input signals and 112 output signals which can be
connected to 56 port pins and 56 MSC interface lines. Additional four inputs for internal
connections (coming from the SCU) and 38 service request outputs are provided.
The LTCA2 module has 40 input signals and 96 output signals that can be connected to
the same 56 port pins as GPTA0 and GPTA1 and 56 MSC interface lines. Additional four
inputs for internal connections (coming from the SCU) and 16 service request outputs
are provided.
Additional connections are described in the following sections.
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