Infineon Technologies TC1796 - Page 1903

TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-248 V2.0, 2007-07
GPTA, V2.0
Figure 24-86 Block Diagram of GPTA Implementation
GPTA0
LTCA2
MSC
Mux
Control
Output
Groups
OG[6:0]
Port
Control
IO
Groups
IOG[6:0]
Interrupt
Control
Clock
Control
Address
Decoder
f
GPTA0
MCB05995
f
CLC
SCU
(Ext.
Request
Unit)
P2.8
P2.15
P3.0
P3.15
P4.0
P4.15
P8.0
P8.7
P9.0
P9.7
MSC0
MSC1
FADC
MultiCAN
ADC0
ADC1
DMA
IN[55:0]
OUT[55:0]
SR
[37:00]
IN[55:0]
OUT
[111:56]
56
IN[39:0]
OUT[39:0]
OUT
[111:56]
SR
[37:00]
SR
[15:00]
GT0xRUN
f
GPTA1
GT1xRUN
f
LTCA2
OUT[111:56]
INT[3:0]
INT[3:0]
INT[3:0]
INT[3:1]
INT0
OUT5
OUT[55:0]
2
GPTA1
8
CLK[7:0]
PLL Clocks
SR15
2
2
2
56
56
40
56
56
56
9
3
8
16
16
8
8
8
16
16
16
8