Infineon Technologies TC1796 - 25.3.3.2 ADC Fractional Divider Register

TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual 25-106 V2.0, 2007-07
ADC, V2.0
25.3.3.2 ADC Fractional Divider Register
The fractional divider register allows the programmer to control the clock rate of the
module timing clock f
ADC
. Both ADCs, ADC0 and ADC1, are controlled by one common
clock control register ADC0_FDR.
ADC0_FDR
ADC Fractional Divider Register (00C
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS
CLK
EN
HW
SUS
REQ
SUS
ACK
0RESULT
rwh rw rh rh r rh
1514131211109876543210
DM SC SM 0 STEP
rw rw rw r rw
Field Bits Type Description
STEP [9:0] rw Step Value
Reload or addition value for RESULT.
SM 11 rw Suspend Mode
SM selects between granted or immediate suspend
mode.
SC [13:12] rw Suspend Control
This bit field determines the behavior of the fractional
divider in suspend mode.
DM [15:14] rw Divider Mode
This bit field selects normal divider mode, fractional
divider mode, and off-state.
RESULT [25:16] rh Result Value
Bit field for the addition result.
SUSACK 28 rh Suspend Mode Acknowledge
Indicates state of SPNDACK signal.
SUSREQ 29 rh Suspend Mode Request
Indicates state of SPND signal.
ENHW 30 rw Enable Hardware Clock Control
Controls operation of ECEN input and DISCLK bit.